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Single-Conversion DVB-H Tuner
The benefit of the automatic DC correction is that it allows
the DC offset to be removed in less than 0.5ms, much
faster than the effective highpass corner frequency of the
correction circuit would otherwise allow. If the DC_SP[1:0]
bits are programmed to 00 prior to exiting hardware shut-
down, the part performs a one-time DC offset cancellation
upon power up then disables the DC correction circuitry
after the power-up sequence completes. This allows for
DC-coupling between the baseband outputs and the
demodulator as long as the receive frequency, baseband
filter setting, and chip temperature stay constant after the
one-time cancellation. A change in these parameters
while the chip is receiving requires recalibration of the DC
offset. However, the typical time-sliced nature of DVB-H
does meet the above requirements for operation with
DC-coupling.
When STBY is connected to V CC , the chip does not follow
the power-up procedure described above, and all circuit
blocks are powered up at the same time. If the
DC_SP[1:0] bits are set to 00 (i.e., quasi-DC-coupled), a
DC calibration is never executed and the MAX2165 is not
functional.
The state of the STBY pin only determines whether or not
DC correction is automatically performed upon exiting
hardware shutdown.
Crystal-Oscillator Interface
The MAX2165 reference-oscillator input can be config-
ured as a crystal oscillator or it can be used as a high-
impedance reference input driven by an external source.
When using an external reference oscillator, drive XB
through an AC-coupling capacitor with a signal amplitude
of approximately 1V P-P and leave XE unconnected. The
phase noise of the external reference must exceed
-140dBc/Hz at offsets of 1kHz to 100kHz.
When connecting directly to a crystal, see the Typical
Application Circuit for the required topology.
Crystal-Oscillator Buffer Output
A buffered crystal-oscillator signal is provided at the
REFOUT pin and can be used to drive the demodulator.
This output requires a DC-blocking capacitor. This buffer
can be enabled or disabled through the SHDN_REF bit in
the Shutdown register (Table 10).
Layout Considerations
The EV kit can serve as a guide for PCB layout. Keep RF
signal lines as short as possible to minimize losses and
radiation. Use controlled impedance on all high-frequen-
cy traces. The exposed paddle must be soldered evenly
to the board’s ground plane for proper operation. Use
abundant vias beneath the exposed paddle for maximum
heat dissipation. Use abundant ground vias between RF
traces to minimize undesired coupling. To minimize cou-
pling between different sections of the IC, the ideal
power-supply layout is a star configuration, which has a
large decoupling capacitor at the central V CC node. The
V CC traces branch out from this node with each trace
going to separate V CC pins of the MAX2165. Each V CC
pin must have a bypass capacitor with a low imped-
ance to ground at the frequency of interest. Do not
share ground vias among multiple connections to the
PCB ground plane.
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